1. Field of the Invention
The present invention relates generally to a crack stop for low K dielectric materials of an integrated circuit (IC) formed on an IC chip using metal interconnects which do not form a self-passivating oxide layer, such as copper or silver interconnects, in a low-K dielectric material such as silicon dioxide SiO2.
More particularly, the subject invention pertains to crack stop structures, and methods for forming the crack stop structures, for preventing damage to the active area of an IC chip, using metal interconnects such as copper or silver interconnects in a low-K dielectric material, caused by chipping and cracking formed along peripheral edges of the IC chip during a dicing operation performed on the IC chip. A moisture barrier or edge seal is formed as a metal stack positioned along the outer peripheral edges of the active area of the IC chip. The crack stop is formed by at least one trench or groove positioned outside of the moisture barrier/edge seal on the outer periphery of the IC chip.
2. Discussion of the Prior Art
During an IC chip dicing operation, cracks form that can propagate into the active area of the IC chip, causing fails. In the prior art, crack stop layers have been incorporated into the perimeter of the IC chip to prevent cracks formed during chip dicing from propagating into the chip. The cracks generally propagate through the BEOL (back end of line) dielectrics which are generally brittle materials such as silicon dioxide SiO2.
In prior art aluminum Al interconnect technology, wherein Al forms a self-passivating oxide layer, the crack stop has been formed as either a metal stack or an etched-out region that surrounds the active circuit area of the chip, and prevents cracks from traversing the BEOL dielectrics into the IC chip.
In prior art copper Cu interconnect technology, the crack stop has been formed as a metal stack that surrounds the active circuit area of the chip to prevent the propagation of cracks from traversing the BEOL dielectrics into the IC chip.
The prior art has also formed a triple edge seal. However the additional edge seal has the disadvantage of taking up more area on the IC chip.